Dual-damascene interconnects without an etch stop layer by alternating ILDs

ABSTRACT

A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

FIELD OF THE INVENTION

[0001] The invention relates to field of fabrication of interconnectlayers in a semiconductor device.

PRIOR ART AND RELATED ART

[0002] In current integrated circuits, several layers of interconnectstructures fabricated above a substrate containing active devices areoften used. Each interconnect layer is fabricated in, or on, aninterlayer dielectric (ILD). Vias are etched in each ILD to make contactwith conductors in an underlying layer. It is generally accepted thatthe dielectric material in each ILD should have a low k to obtain lowcapacitance between the conductors. Often the low k dielectrics have lowdensities and etch quite rapidly. Particularly for unlanded contacts,over etching can occur and extend into an underlying layer causing adefect. For this reason, etchant stops are formed between each layer.Unfortunately, these etchant stop layers typically have higher k values,and thereby increase the capacitance between conductors.

[0003] The problem is shown in FIG. 1 where a first ILD 10 includes acopper conductor and via fabricated with a dual damascene process. Whenan opening 12 is etched into the next ILD 11, the layer 13 acts as anetchant stop to prevent etching into the underlying ILD 10. But for thelayer 13, the region shown by the dotted line 14 may be etched awaycausing a defect. Consequently, the layer 13 is needed even though itincreases the capacitance between conductors.

[0004] Typically the layer 13 acts both as an etchant stop and as adiffusion barrier. Layer 13's role as an etchant stop is the majorcontributor to the capacitance since a layer thickness of 800-1600 Å isoften used for the etchant stop function compared to only 200 Å neededto provide the barrier function.

[0005] Another technology that may be used instead of using the layer 13of FIG. 1 as a barrier layer is to use a shunt layer with cobalt ornickel or an alloy thereof. This involves the selection deposition of ashunting material over the copper lines to present electromigration intothe overlying ILD. This is discussed in co-pending application Ser. No.09/753,256; Interconnect Structures and a Method of ElectrolessIntroduction of Interconnect Structures, assigned to the assignee of thepresent application, filed Dec. 28, 2000.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a cross-sectional elevation view showing two levels ofan interlayer dielectric (ILD) as used in the prior art.

[0007]FIG. 2 is a cross-sectional elevation view showing two ILDs asfabricated in accordance with an embodiment of the present invention.

[0008]FIG. 3 is a cross-sectional elevation view showing several ILDsfabricated with an embodiment of the present invention.

DETAILED DESCRIPTION

[0009] An integrated circuit interconnect structure and process forfabricating the structure is described. In the following description,numerous specific details are set forth such as specificinterlayerdielectrics (ILD) materials in order to provide a thorough understandingof the present invention. It will be apparent to one skilled in the artthat the present invention may be practiced without these specificdetails. In other instances, well known processing steps, such asetching and deposition steps, are not described in detail in order notto unnecessarily obscure the disclosure.

[0010] The present invention uses at least two different ILD materialswhich are alternated from one interconnect level to the next. Thematerials are selected such that each of the materials is etchable morerapidly in the presence of the other material. In one embodiment, thefirst material is an organic low k dielectric such as a polymer baseddielectric and the second material is an inorganic material such acarbon-doped oxide.

[0011] The first category of materials, the organic polymers, aretypically spun-on. A discussion of perfluorocyclobutane (PFCB) organicpolymers is found in “Integration of Perfluorocyclobutane (PFCB)”, by C.B. Case, C. J. Case, A. Komblit, M. E. Mills, D. Castillo, R. Liu,Conference Proceedings, ULSI XII.COPYRGT. 1997, Materials ResearchSociety, beginning at page 449. These polymers are available fromcompanies such as Dupont, Allied Signal, Dow Chemical, Dow Corning, andothers.

[0012] The second category of materials that may be used in the presentinvention are silica-based such as the nanoporous silica aerogel andxerogel. These dielectrics are discussed in “Nanoporous Silica forDielectric Constant Less than 2”, by Ramos, Roderick, Maskara and Smith,Conference Proceedings ULSI XII.COPYRGT. 1997, Materials ResearchSociety, beginning at page 455 and “Porous Xerogel Films as Ultra-LowPermittivity Dielectrics for ULSI Interconnect Applications”, by Jin,List, Lee, Lee, Luttmer and Havermann, Conference Proceedings ULSIXII.COPYRGT. 1997, Materials Research Society, beginning at page 463.

[0013] Assume for sake of discussion that a process has six levels ofmetalization, identified as ILDs 0-5. While the present invention insome cases may be used in all of the six levels of ILD, in oneembodiment it is used for levels 1-4. The 0 level ILD generally contactsthe substrate and may require different processing such as discussed inU.S. Pat. No. 6,124,191. The uppermost ILD level typically receivesspecial processing for packaging purposes such as the inclusion ofbumps, and for this reason, an undoped silicon dioxide layer may beused.

[0014] Referring to FIG. 3, the structure for four consecutive ILDlevels 30, 31, 32, and 33 is illustrated. These levels may be levels 1-4in a six level metalization process. Levels one and three are formedfrom a first ILD material which may be, for instance, a low kcarbon-doped oxide. The alternate layers 31 and 33, as indicated, arefabricated from a second ILD material such as a polymer baseddielectric.

[0015] As shown is FIG. 3, vias and conductors are formed in each of theILDs 30-33. These vias and conductors may be formed in an ordinary wayusing, for instance, a dual-damascene process. In this case, both thevias and conductors may, for instance, be fabricated from a copper orcopper alloy which is enclosed within a conductive barrier material toprevent the copper from diffusing into adjacent dielectric materials.

[0016] In FIG. 3, a barrier layer of silicon nitride or silicon carbide34 is used between the ILDs. This dielectric presents the copper fromdiffusing into the ILDs. Layer 34, as mentioned above, may be relativelythin (e.g. 200 Å) since it is not used as an etchant stop. Thus, it doesnot add to the interconnector and interconductor capacitance to theextent that the thicker etchant stop would.

[0017] In FIG. 2, some of the processing used to fabricate a structurefor one embodiment is illustrated. First ILD 19 is fabricated from afirst material such as the polymer based dielectric and includes viasand conductors. A shunting layer 25 is added over the copper conductorsto present electromigration for this embodiment. Then ILD 20 is formedfrom a second dielectric material such as the carbon-doped oxide. Viasand conductors are fabricated in ILD 20 along with the shunting layer25. All of this is done with known processing steps.

[0018] Now an ILD 21 is formed directly on ILD 20 without anintermediate etchant stop such as layer 13 of FIG. 1. ILD 21 isfabricated from a first material such as the polymer based dielectric.

[0019] Patterning is used for each layer to define the via and conductoropenings such as with a sacrificial light absorbing material (SLAM) or adual hard masked process to form the opening 24 and like openings or acombination of these steps. The opening 24, is used to form a contactand conductor.

[0020] In FIG. 2, a shunting material is used to provide a barrierwhereas in FIG. 3, a dielectric is used for the barrier. Both may beused at the same level in the ILDs or they may be alternated. Forinstance, often the shunting material has been deposited, the barrierdielectric may be formed. An opening is etched in the dielectric for avia when the via/conductor openings are etched for the overlying ILD.

[0021] Importantly, with the disclosed embodiment, the first materialetches with a first etchant more rapidly than the underlying secondmaterial of the ILD 20. Preferably the differential etching rate is 20to 1, or greater. Thus, when the opening 24 is etched, and the etchantreaches the second material, very little etching occurs in the ILDsecond material. For this reason, the defect shown by the dotted line 14of FIG. 1 does not occur even though there is no etchant stop.

[0022] Similarly, when the openings were etched in the ILD 20, anetchant is used that etches the second material more rapidly than thefirst material. Thus, when an opening was etched in the ILD 20, theetchant did not etch into the underlying first material. Again it ispreferred that the etchant used to etch the first material etches thismaterial at a rate at least 20 times faster than the first material.

[0023] While in one embodiment all the even number ILD levels are madefrom a first material and all the odd number ILD levels are made from asecond material, this is not necessary. Each layer may have a differentmaterial a long as a layer can be etched at a higher rate than theunderlying layer. However, it maybe more cost effective for all the oddnumbered layers to be made of a first material and all of the evennumbered layers to be made of a second material.

[0024] The inorganic materials discussed above may be etched withfluorocarbon such as C₄F₈, C₅F₈, C₂F₆, C₄F₆, CF₄ or CH₂F₂. Thefluorocarbon is typically used in a mixture with oxygen and argon. Aselective of 20 to 1 is achievable between the inorganic or organic ILDsdiscussed above.

[0025] The organic polymers discussed above may be etched with hydrogenor oxygen which in effect bums the polymer in a mixture with nitrogen. Aselective of 30 to 1 is achievable between the organic and inorganicdielectrics.

[0026] Thus, ILDs with reduced capacitance has been disclosed.

What is claimed:
 1. An integrated circuit comprising: a first interlayerdielectric layer (ILD) of a first material, the first material having afirst etchant rate when exposed to a first etchant; a second ILD of asecond material disposed on the first ILD, the second ILD having anetchant rate slower than the first etching rate when exposed to thefirst etchant; a third ILD disposed on the second ILD of the firstmaterial.
 2. The integrated circuit defined by claim 1 wherein thesecond material etches more rapidly than the first material when exposedto a second etchant different than the first etchant.
 3. The integratedcircuit defined by claim 2 wherein the first material comprises anorganic based dielectric.
 4. The integrated circuit defined by claim 3wherein the second material comprises a nonorganic based dielectric. 5.The integrated circuit defined by claim 1 including a fourth layerdisposed on the third layer fabricated from the second material.
 6. Theintegrated circuit defined by claim 5 wherein the first materialcomprises a polymer based dielectric.
 7. The integrated circuit definedby claim 6 wherein the second material comprises a carbon-doped oxide.8. An integrated circuit comprising: first interlayer dielectrics (ILDs)disposed alternately between second ILDs; the first ILDs being etchableat a higher rate than the second ILDs by a first etchant; the secondILDs being etchable at a higher rate than the first ELD's by a secondetchant.
 9. The integrated circuit defined by claim 8 where the firstILD include first conductors and first vias.
 10. The integrated circuitdefined by claim 9 wherein the second ILD's include second conductorsand second vias.
 11. The integrated circuit defined by claim 10 whereinthe first ILDs comprise a polymer based dielectric.
 12. The integratedcircuit defined by claim 11 wherein the second ILDs comprise acarbon-based oxide.
 13. An integrated circuit comprising: firstinterlayer dielectrics (ILDs) disposed alternatively between second ILDsof first and second materials, respectively, wherein each of the firstand second materials are etchable at faster rates than the other in thepresence of different etchants.
 14. The integrated circuit defined byclaim 13 wherein the first ILDs include first conductors and first vias.15. The integrated circuit defined by claim 14 wherein the second ILDsinclude second conductors and second vias.
 16. The integrated circuitdefined by claim 13 wherein the material for the first ILDs comprises anorganic based dielectric.
 17. The integrated circuit defined by claim 16wherein the material for the second ILDs comprises a non-organic baseddielectric.
 18. An integrated circuit comprising: a first interlayerdielectric (ILD); a second ILD disposed over the first ILD, the secondILD being etchable at a faster rate than the first ILD by a firstetchant; a third ILD disposed over the second ILD, the third ILD beingetchable at a faster rate than the second ILD by a second etchant. 19.The integrated circuit defined by claim 18 wherein the first and thirdILDs are fabricated from a first material.
 20. The integrated circuitdefined by claim 18 including a fourth ILD disposed over the third ILD,the second and fourth ILDs being fabricated from a second material. 21.The integrated circuit defined by claim 18 including conductors and viasin each of the ILD layers.
 22. The integrated circuit defined by claim20 wherein the first and third ILDs are fabricated from a polymer baseddielectric.
 23. The integrated circuit defined by claim 22 wherein thesecond ILD is fabricated from a carbon-based oxide.
 24. The integratedcircuit defined by claim 20 wherein the first and third ILDs arefabricated from a carbon-based oxide and the second and fourth ILDs arefabricated from a polymer based dielectric.
 25. A method for fabricatingan integrated circuit comprising: depositing a first ILD; forming viasand conductors in the first ILD; forming a second ILD directly on thefirst ILD; etching openings in the second ILD with an etchant thatetches the second ILD faster than the first ILD; forming a third ILDdirectly on the second ILD; and etching openings in the third ILD withan etchant that etches the third ILD faster than the second ILD.
 26. Themethod defined by claim 25 wherein the second ILD comprises acarbon-based oxide.
 27. The method defined by claim 26 wherein the thirdILD comprises a polymer based dielectric.
 28. The method defined byclaim 27 wherein the second ILD is etched with a fluorocarbon.
 29. Themethod defined by claim 28 wherein the third ILD is etched with oxygenor hydrogen.
 30. The method defined by claim 25 including the steps offorming vias and conductors in the second and third ILDs.
 31. A methodof fabricating an integrated circuit comprising: forming first alternateinterlayer dielectrics (ILDs) of a first material; forming second ILDsintermediate between the first ILDs of a second material where thesecond ILDs are etchable at a faster rate than the first ILDs by a firstetchant and where the second ILDs are etchable at a faster rate than thefirst ILDs by a second etchant.
 32. The method defined by claim 31wherein the first material comprises an organic based material, andwherein the second material comprises a non-organic based material. 33.The method defined by claim 32 including forming vias and conductors ineach of the ILDs.
 34. The method defined by claim 33 wherein the viasand conductors are formed with a dual-damascene process.
 35. The methoddefined by claim 31 wherein the first and second layers are separated bya barrier dielectric.
 36. The method defined by claim 31 whereinconductors in the first and second layer are covered by a shuntingmaterial.